CMOS Open-Fault Detection in the Presence of Glitches and Timing Skews

Ahsfracf -Two-pattern or multipattern test sequences may fail to detect CMOS stuck-open faults in the presence of glitches. The available methods to augment CMOS gates for testing stuck-open faults are found to be inadequate in the presence of glitches. A new testable CMOS design technique is presented. Some extra transistors are used in such a way that the CMOS gate is converted to a pseudo nMOS/pMOS gate during testing. With the proposed design technique, CMOS open faults can be detected regardless of timing skews/delays, glitches, or charge sharing among the internal nodes. The major advantage of the proposed testable design technique is that it allows the use of a single test vector to detect a stuck-open fault. This significantly reduces the complexity of test generation and the time consumed for testing. The design procedure is simple and all the classical algorithms and automatic test-pattern generating programs (ATPG’s) can be used to generate tests for circuits designed according to this new technique. Even random testing techniques can be used efficiently to detect the open faults in these CMOS circuits.